Pakiet: covered-doc (0.7.10-3.1)

[ Pakiet źródłowy: covered  ]

Verilog code coverage analysis tool - documentation

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

This package contains the documentation.

Znaczniki: Rola: Dokumentacja

Pobieranie covered-doc

Pobierz dla wszystkich dostępnych architektur

Architektura	Rozmiar pakietu	Rozmiar po instalacji	Pliki
all	1 650,8 KiB	2 439,0 KiB	[lista plików]