[ Bron: opensta ]
Pakket: opensta-dev (0~20191111gitc018cb2+dfsg-1)
Verwijzigingen voor opensta-dev
Debian bronnen:
Het bronpakket opensta downloaden:
- [opensta_0~20191111gitc018cb2+dfsg-1.dsc]
- [opensta_0~20191111gitc018cb2+dfsg.orig.tar.xz]
- [opensta_0~20191111gitc018cb2+dfsg-1.debian.tar.xz]
Beheerders:
Externe bronnen:
- Homepage [github.com]
Vergelijkbare pakketten:
Gate-level Static Timing Analyzer - development files
After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a Tcl interface for entering commands for analysing designs.
It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design.
This package contains the header files and some libraries for development.