Package: yosys (0.23-6)

[ Source: yosys  ]

Framework for Verilog RTL synthesis

This is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base.

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• dep: libffi8 (>= 3.4)

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• dep: libstdc++6 (>= 11)

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Architecture	Package Size	Installed Size	Files
amd64	3,170.5 kB	13,599.0 kB	[list of files]