Paketti: yosys-dev (0.8-1)

[ Source: yosys  ]

Framework for Verilog RTL synthesis (development files)

Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base.

This package contains the headers and programs needed to build yosys plugins.

Imuroi yosys-dev

Imurointi kaikille saataville arkkitehtuureille

Arkkitehtuuri	Paketin koko	Koko asennettuna	Tiedostot
amd64	56.9 kt	312.0 kt	[tiedostoluettelo]
arm64	56.9 kt	312.0 kt	[tiedostoluettelo]
armhf	56.9 kt	312.0 kt	[tiedostoluettelo]
i386	56.9 kt	312.0 kt	[tiedostoluettelo]