Package: iverilog (12.0-2 and others) [debports]

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Icarus verilog compiler

Icarus Verilog is intended to compile all of the Verilog HDL as described in the IEEE-1364 standard. It is not quite there yet. It does currently handle a mix of structural and behavioral constructs.

The compiler can target either simulation, or netlist (EDIF).

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Download iverilog

Download for all available architectures

Architecture	Version	Package Size	Installed Size	Files
sparc64 (unofficial port)	12.0-2+b1	1,669.3 kB	25,160.0 kB	[list of files]